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NXP Semiconductors /LPC408x_7x /UART1 /RS485DLY

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Interpret as RS485DLY

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DLY0RESERVED

Description

RS-485/EIA-485 direction control delay.

Fields

DLY

Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data